address may or may not have the same name. In the CPU parameters description in the
following sections, only "active" bits are mentioned. All "non-active" bits should be written
with B?0? or return B?0? when read. It would be prudent for the CPU SW to ignore the values
read for of non-active bits. Non-active addresses should not be written to or read from at all.
CPU SW is responsible for user interface and player control, internal units set-up and control,
navigation and high level front end functions.
The CPU interfaces with the following external entities using GPIO functions: IR remote
control receiver; Audio ADCs and DACs; Other player chips and debug
aids.
2.8 PDU - Picture Decoding Unit
The PDU unit is mainly responsible for the decoding MPEG video streams and reconstructing
the coded frames. It is made of two main parts: A dedicated programmable processor (DVP)
and a dedicated HW called PRU (picture reconstruction unit).
The DVP has a 16 bit data ALU with 6K of 20 bit instructions RAM and 1 KWords data RAM.
The DVP has a HW Huffman VLC decoder (HDC) containing all fixed Huffman tables for
decoding of MPEG 4, DivX, MPEG 1 and MPEG 2 video. The DVP receive video code from
the MCU into a 2400 bit video code FIFO, parse all consecutive sequence, GOP and
picture/VOP headers and extensions, store some of the parameters and transfer some of the
parameters to the CPU through its P_Bus (parameter bus, not to be confused with the ADP
peripheral bus) and a CPU interface unit.
The frame decoding is shared between the DVP and the PRU. For each macroblock, the DVP
decodes its header (together with a preceding slice/GOB header when needed), extract the
parameters and control (through the P_Bus) the PRU that reconstruct the 6 blocks of the
macroblock. The PDU is using the MCU to retrieve forward and backward macroblocks and
store the reconstructed macroblock. During the macroblock decoding and reconstruction, the
DVP and PRU time share the video code FIFO and HDC. First they are used by the DVP and
then by the PRU. The specific SDRAM buffers designated for reference retrieval and
reconstructed image storage are indicated by the DVP. The time sharing and block decoding
timing are controlled by timing signals (mb_go and 6 b_go) generated by the MCU.
The PRU is made of three units (the de-scaling and de-quantizing unit followed by the IDCT
unit which is followed by the reconstruction unit) operating on each block in a pipeline fashion.
The PRU starts to operate in parallel to the blocks decoding and finishes the operation in
parallel to the next macroblock header decoding by the DVP. The PRU is using several
single port RAMs. The PRU has interface to the ADP that can use the PRU for JPEG decoding
dequantization and IDCT steps.
The HDC have some coded bitstream error detectors, and an MPEG video "start code prefix"
searcher. The rest of the error decoding and all error recovery and concealment are the
responsibility of the DVP SW that may notify the CPU SW for further handling.
The PDU receive timing signals from the VPU and MCU.
The other task of the DVP SW is de-multiplexing of system bitstream into elementary
bitstreams: video, audio, and navigation, sub-picture ((for DVD) or sub-titles (for DivX). The
elementary stream IDs can be changed on the fly. The two SW tasks (one called the ?video?
task and the other called alternately ?de-mux? or ?system? task) are switched once at the
beginning of the macroblock period from the de-mux task to the video decoding task and again
to de-mux task after the video decoding task finished its job for that macroblock. The
multiplexed bitstream is received from the BSI. The resulting elementary streams are stored
back in separate buffers in the SDRAM to be used by the other task of the PDU (video |
ACEC
