- Direct interface (through RF and servo amplifiers) to several types of disc loaders.
- SW controlled GPIO to interface to IR remote control receiver, front panel concentrator,
audio DACs and ADC, etc.?, e.g., using I2C, SPI, DDC (HDMI) and other protocols.
- 3 line serial general purpose slave interface (SSC).
- 2 UART interfaces for CPU SW debug.
- JTAG interfaces for CPU, ADP and DSP SW debug.
1.2.5 Physical Features
- Dual supply: 1.8V for the core and PLL, and 3.3V for the I/O and DACs.
- 208 pin, PQFP pin compatible with Vaddis 770.
- TTL I/O levels. 5V tolerance on many inputs.
- Single 27 MHz crystal/clock generator input.
- Less than 1.6 W power consumption during operation.
- Several power-down modes, including minimal power standby mode.
The pins used for disc loader and NOR flash interface have a second function for direct flash
card reading (not shown). Interface to an HD TV monitor is through an HDXtreme companion
chip (not shown). When needed, the 64 Mbits SDRAM can be replaced by a 128 Mbits
SDRAM.
2 Functional Description
2.1 External interface
The main external interfaces of the Vaddis 778 are shown in the next figure. Interface to an HD
TV monitor is through an HDXtreme companion chip (not shown).
2.2 AFE - Analog Front End Unit
The AFE unit handles two functions: High frequency RF signal (from an RF amplifier device)
sampling for the data bitstream recovery and (up to 8) low frequency error and RF ?envelope?
signals sampling for the servos. Two other functions are assumed to be handled by the RF
amplifier device: Laser power generation and stabilization (ALPC) and reference voltages
generation for the OPU.
The RF signal utilized for the data bitstream recovery is sampled using a high speed ADC,
preceded by a level shifter and a PGA (programmable gain amplifier). The converted digital
signal is further processed in the DRC unit.
The converted digital signals are further processed by the DSP.
2.3 DRC - Digital Read Channel
Processing Unit
The DRC is a HW unit that receive the "RF" converted digital signal from the AFE and process
it by HW. The result of the processing is a "raw" bitstream that is transferred to the STP for
further processing, a bit-rate signal that is transferred to the SERVO unit for spindle control
and lock and defect indication signals. A level measuring HW (called AGC after its intended
usage) measure (alternately) the min and max levels of the input signal from the AFE and the
result helps the DSP set the values of the bias and gain in the AFE.
2.4 ECC - Error Correction Unit
For CD discs, the ECC unit reads media data form the SDRAM through the MCU and
performs error corrections ("EC") of the frames (C1/C2) and de-scrambling. For some CD disc
types, further (P/Q, sector based) EC is performed and then the EDC function. All error
correction is done on the bitstream stored in the ECC unit.
The number of P/Q EC passes (on rows and columns alternating) is adaptive. EC and ED
"statistics" can be read by the CPU for "re-try" or other error handling and track buffer
management decisions. The relevant parts of the corrected bitstream and error indications |
ACEC
