(6-6) Register in Decrypt IC (IC811)(7-3) Reset Line in 64020
Register write ? Register read matching checkRegister write ? Hard reset ? Register read matching check
Error 05: Write/read data mismatch errorError 02: Reset error
05: Write/read data mismatch error
0x00 � 0xfc data (lower 2 bits are masked) are written to the inter-
rupt register, then read to check for matching.After O0xff� is written to the Capture/Compare Control Register
If write/read mismatch error occurred, checking can be repeated.0, whether it is initialized to O0x00� by the reset pulse signal is
checked.
(6-7) Reset of Decrypt IC (IC811)To make sure, the written data is read to check for matching be-
fore reset is executed.
Register write ? Hard reset ? Register read
(7-4) DREQ Signal Line in 64020
Error 02: Reset error
05: Write/read data mismatch errorAV Decoder (IC203) DMA check
After O0xfc� is written to the interrupt registerError, whether it is ini-03: Data write error
tialized to O0x00� by the reset pulse signal is check04: Data read errored.
To make sure, the written data is read to check for matc05: Write/rhing be-ead data mismatch error
fore reset is executed.06: DMA transfer DREQ error
07: DMA transfer address error
(6-8) Interrupt Line in Decrypt IC (IC811)
The connection of DREQ signal line to the AV Decoder (IC203)
ROM (IC803) ? ARP (IC806) ? Decrypt (IC811)is checked through DMA transfer.
If no error is found in DMA transfer, the transferred data are com-
Error 22: Decrypt (IC811) interruption is not detectedpared with the DRAM (IC810) data read from the register.
AC-3 audio data stored in ROM (IC803) are transf(7-5) DRAM in 64020erred to the
Decrypt via ARP (IC806), then the reserved data interruption from
Decrypt (IC811) is detected.ROM data ? AV Decoder (IC203) ? DRAM (IC810) ? AV De-
To discriminate the ARP (IC806) interruption whiccoder (IC203) read matching checkh is alsosent in
the same line, the ARP (IC806) interruption is allmasked.
Error 03: Data write error
(6-9) Reserved Data Head Byte Reading04: Data read error
05: Write/read data mismatch error
ROM (IC803) ? ARP (IC806) ? Decrypt (IC811) reserved data06: DMA transfer DREQ error
head byte read matching check07: DMA transfer address error
Error 05: Write/read data mismatch errorROM (IC803) patterns are copied to all areas to be checked. Be-
22: Decrypt interruption is not detectedcause of large DRAM (IC810) capacity, each time 256 bytes are
copied, the addresses of copy source (ROM) are returned by 255
AC-3 audio data stored in ROM (IC803) are transfbytes. In detail check,erred to the to verify all bits in DRAM (IC810), the bit
Decrypt via ARP (IC806), then the reserved data head bpatterns arytes aree checked again after inversion. DMA is used when
read from Decrypt (IC811) register.writing/reading the data. Though the bus width of AV Decoder
As this audio data consists of 5 sectors, 0, 1, 2, 3, 4 data are writ-(IC203) is 64 bits, the display is given in 8 bits. Namely, actual
ten at the head of reserved data of respective sectors.address is 1/8 of displayed data, and lower 3 bits indicate the byte
Whether these data are matched is checked through eposition.very sector
interruption.Overwriting by the shadow can be detected, as the data are written
If write/read mismatch error occurred, checking can be repeated.to all areas, then read. In the detail check, all areas of RAM are
checked twice by inverting the data, while in the simple check one
(7) AV Decoder (IC203)block is checked, then subsequent 4 blocks are skipped, and also
inverted data are not checked.
(7-2) Register in 64020If write/read mismatch error occurred, checking can be repeated.
Register write ? Register read matching check
Error 05: Write/read data mismatch error
O0x00� � O0xff� data are written to 51 registers where all bits can
be written/read, then they are read to check for matching.
If write/read mismatch error occurred, checking can be repeated.
6-4 |
ACEC
