Pin No.Pin nameI/ODescription
DA16 output when PSSL=OH�, 48-bit slot serial data output when PSSL=OL�
46DATAO(PSSL (pin $L)=fixed at OL�) Serial data output to the D-RAM controller (IC681) and
MPEG audio/video decoder (IC701).
DA15 output when PSSL=OH�, 48-bit slot bit clock signal output when PSSL=OL�
47BCLKO
(PSSL (pin $L)=fixed at OL�) Bit clock signal (2.8224 MHz) output to the D-RAM
controller (IC681) and MPEG audio/video decoder (IC701).
DA14 output when PSSL=OH�, 64-bit slot serial data output when PSSL=OL�
4864 DATAO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA13 output when PSSL=OH�, 64-bit slot bit clock signal output when PSSL=OL�
4964 BCLKO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA12 output when PSSL=OH�, 64-bit slot L/R sampling clock signal output when
5064 LRCKO
PSSL=OL� (PSSL (pin $L)=fixed at OL�). Not used (open)
DA11 output when PSSL=OH�, GTOP signal output when PSSL=OL�
51GTOPO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA10 output when PSSL=OH�, XUGF signal output when PSSL=OL�
52XUGFO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA09 output when PSSL=OH�, XPLCK signal output when PSSL=OL�
53XPLCKO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA08 output when PSSL=OH�, GFS (guard frame sync) signal output when PSSL=OL�
54GFSO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA07 output when PSSL=OH�, RFCK (read frame clock) signal output when PSSL=OL�
55RFCKO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA06 output when PSSL=OH�, C2PO signal output when PSSL=OL�
56C2POO(PSSL (pin $L)=fixed at OL�) C2PO signal output to the D-RAM controller (IC680)
and MPEG audio/video decoder (IC901).
DA05 output when PSSL=OH�, XRAOF (RAM over flow) signal output when PSSL=OL�
57XRAOFO
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA04 output when PSSL=OH�, MNT3 (monitor 3) signal output when PSSL=OL�
58MNT3O
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA03 output when PSSL=OH�, MNT2 (monitor 2) signal output when PSSL=OL�
59MNT2O
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA02 output when PSSL=OH�, MNT1 (monitor 1) signal output when PSSL=OL�
60MNT1O
(PSSL (pin $L)=fixed at OL�). Not used (open)
DA01 output when PSSL=OH�, MNT0 (monitor 0) signal output when PSSL=OL�
61MNT0O
(PSSL (pin $L)=fixed at OL�). Not used (open)
62XTAIIMaster clock signal (16.9344 MHz) input from the D/A converter (IC322).
63XTAOOMaster clock output terminal (16.9344 MHz). Not used (open)
64XTSLIMaster clock selection input terminal (fixed at OL�).
65DVSS�Ground terminal (digital system).
66FSTII2/3 divider input terminal of pins ^a (XATI) and ^L (XTAO).
67FSTOO2/3 divider output terminal of pins ^a (XATI) and ^L (XTAO).
68C4MO4.2336 MHz clock signal output terminal. Not used (open)
69C16MO16.9344 MHz clock signal output terminal. Not used (open)
70MD2IDigital out on/off control signal input terminal Fixed at OH� in this set.
71DOUTODigital signal (for coaxial out and optical out) output terminal. Not used (open)
72EMPHOEmphasis control signal output terminal. Not used (open)
73WFCKOWrite frame clock signal output terminal. Not used (open)
Sub-code sync (S0+S1) detection signal output to the D-RAM controller (IC681) and
74SCORO
system controller (IC801).
75SBSOOSub-code P-W serial data output terminal. Not used (open)
� 13 � |
ACEC
