Servo control
Servo CPU uses 16-bit CPU. The operating clock is 20 MHz.
Servo CPU performs the following processing.
. Controls various motor drivers (capstan, reels, and drum).
. Detects each FG signal, PG signal, and sensor state.
. Generates each mode signal and timing pulse corresponding to the tape transport state.
. Controls the addresses of each JOG memory on the VPR-47 board and the DPR-118 board.
. Processes communications with drum MPU (head select control MPU).
. Processes communications with DT MPU (bimorph (DT) heads control MPU for analog Betacam PB
operation).
Each communication between SYS1 CPU and SYS2 CPU, SYS2 CPU and servo CPU, and servo CPU
and DT MPU is performed via the dual port RAM.
(7) SDTI (SX) Output System (Option) (DPR-119 Board)
SDTI (SX) output processing is performed on the DPR-119 board (BKNW-118).
The video signal data and audio signal data that are output from the DPR-118 board as SDTI output
signal data are packed by the video and audio data pack blocks on the DPR-119 board.
The packed signal data is passed through an SDTI (SX) interface block and converted from parallel to
serial. The converted signal data is then output from the connector panel as the SDTI (SX) output signal.
(8) SDTI-CP Output System (Option) (DPR-150 Board/BKNW-124)
SDTI-CP output processing is performed on the DPR-150 board (BKNW-124).
The video signal data output from the DPR-118 board as SDTI-CP output signal data is performed a
transformation coding (transforms a IB stream into an I only stream) by the transcode block. The video
signal data is converted to MPEG stream by SX-to-MPEG block. The converted video signal data is send
to the SDTI-CP pack block.
The audio signal data is send to the SDTI-CP pack block through the audio I/F block.
The video signal data and audio signal data input to the SDTI-CP pack block are packed to the SDTI-CP
format. The packed signal data is then output from the connector panel as the SDTI-CP output signal after
converting from parallel to serial.
On the DPR-150 board, SYS3 CPU is mounted for controlling.
SYS3 CPU used RISC CPU, and the operating clock is 40 MHz.
Communication between SYS3 CPU and SYS2 CPU (SS-83 board) is performed via the inner dual port
RAM of SYS3 CPU.
DNW-A65/A65PB-5 |
ACEC
