D-NE500/NE506CK
SECTION 5
DIAGRAMS
5-1. IC PIN DESCRIPTIONS
Y IC601 CXD3039AR (RF AMP, DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, D-RAM CONTROLLER)
(MAIN BOARD (1/2))
Pin No.Pin NameI/OPin Description
1XRASORow address strobe signal output to the D-RAM
2XWEOData input enable signal output to the D-RAM
3 to 6D1, D0, D3, D2I/OTwo-way data bus with the D-RAM
7DCLKONot used
8DCKEONot used
9XCASOColumn address strobe signal output to the D-RAM
10WFCK/DQMOWFCK signal output terminal Not used
11 to 13A9 to A7OAddress signal output to the D-RAM
14DVSSNGround terminal (for D-RAM interface)
15 to 17A6 to A4OAddress signal output to the D-RAM
18XRDEID-RAM read enable signal input terminal
19VDD0NPower supply terminal (digital system)
20CLOKISerial data transfer clock input from the system controller
21SDTOISerial data input from the system controller
22SENSOSerial data output to the system controller
23XLATISerial data latch pulse signal input from the system controller
24XSOEISerial data output enable signal input from the system controller
25SYSMIAnalog muting on/off control signal input OH�: muting on
26WDCKOGRSCOR signal output to the system controller Not used
27SCOROSubcode sync (S0+S1) detection signal output to the system controller
28XRSTIReset signal input from the system controller OL�: reset
29PWMIISpindle motor external control signal input terminal Not used
30XQOKISubcode Q OK signal input terminal Not used
31XWREID-RAM write enable signal input terminal Not used
32R8MOSystem clock output to the system controller
33VSS0NGround terminal (digital system)
34SQCKISQSO readout clock input terminal Not used
35SCLKISENS serial data read clock input terminal Not used
36SQSOOCD text data output terminal Not used
37XEMPOD-RAM read prohibition signal output terminal Not used
38XWIHOD-RAM write prohibition signal output terminal Not used
39SBSOOSubcode P to W serial data output terminal Not used
40EXCKOSQSO readout clock output terminal Not used
41XTSLIInput terminal for the system clock frequency setting Not used
42HVSSNGround terminal (for headphone)
43HPLOPDM signal output for L-ch headphone to the headphone amplifier Not used
44HPROPDM signal output for R-ch headphone to the headphone amplifier Not used
45HPVDDNPower supply terminal (for headphone)
46XVDDNPower supply terminal (for master clock)
47XTAIISystem clock input terminal (16.9344 MHz)
48XTAOOSystem clock output terminal (16.9344 MHz)
49XVSSNGround terminal (for master clock)
50AVDD1NPower supply terminal (analog system)
51AOUT1OL-ch analog audio signal output
52VREFLOL-ch reference voltage output terminal
53, 54AVSS1, AVSS2NGround terminal (analog system)
55VREFROR-ch reference voltage output terminal
56AOUT2OR-ch analog audio signal output
10 |
ACEC
