Front Panel and Front Panel Controller BoardQuad SHARC Processor Board
The front panel controller has two processors:The Quad SHARC processor board contains four
the 89C52 8-bit microcontroller and the ADSP2115 16-bitADSP21061 (SHARC) 32 bit floating point processors
fixed-point digital signal processor (DSP).used for audio processing of 16 channels of audio.
All four SHARCs operate at a 40 MHz clock rate.
The 89C52 controls all the front panel buttons, individualSince the SHARC code is downloaded to internal memory
LEDs, and the 2 line x 20 character VF display;from the PC mother board, it can be field upgraded via the
it is connected to LED driver logic, switch scan logic,DADR software upgrade utility.
encoder wheel logic and an interface to the DSP processor.
The microcontroller gets commands from the PC motherAudio data is input and output using the TDM formal of
board via the COM1 serial communication portthe serial ports of the ADSP21061.
115 kbits/sec and notifies the PC motherboard of buttonThere are two TDM audio signal streams with 8 channels
presses.per signal (2 serial ports are used).
The 89C52 is programmed via a built-in PROM which isThe audio data is stored in the dual port DRAM where the
not field re-programmable.SCSI board(s) or Pentium PC and the SHARC processors
can access it simultaneously.
The ADSP2115 DSP operates at 25 MHz and is programmedThe SHARCs continuously store all incoming data in
via 32 k x 8 PROM that is not field re-programmable.DRAM, and continuously read two subchannels per
The DSP converts the audio TDM stream to a 16-channelchannel for event crossfades. This enables the seamless
meter indication.punching required for dubbing. Incoming data is gain
Each channel has an average level displayed as well as aadjusted and packed into 32 bit words prior to storage in
peak level indication.DRAM(16,20, and 24 bits data is supported). The incom-
Peak levels are updated every 0.1 seconds and are held foring data is also analyzed for capture of waveform data,
1.5 seconds. A fast attack slow decay algorithm is used towhich is also stored in DRAM.
derive the average audio level.Playback data is unpacked, crossfaded (the two subchannels
The DSP sets the column address and row data registers inare mixed into one), and rate filtered.
the meter interface logic that determines the LED patternThe input and playback data are crossfaded for glitch
to be displayed.elimination during recording and an output gain is applied.
The 16 x 16 array of LEDs are scanned left to right by theThe data is then output to the TDM streams.
DSP at a fast rate (about 100 times/second) to avoidThe SHARC processors also handle the GPI/GPO process-
flicker.ing, DRAM buffer management and Pentium PC command
The DSP also adds all 16 audio channels together to form aprocessing.
mono mix to be sent to the headphone digital to analog
converter. Based on commands from the 89C52, theThe AES reference is also provided on the board to allow
relative gain levels of each channel are changed to respondthe DSP code to acquire the time of day (TOD) informa-
to the solo buttons on the front panel.tion carried with the DADR AES reference.
When one channel is selected, the gain is maximized forThis allows the audio to be started and stopped on an exact
the selected channel. When more than one channel isaudio sample relative to other DADRs.
selected, the gain is reduced to avoid clippingThe AES reference interface is also used to derive a master
the headphone output.audio clock at 256*Fs (12.288 MHz at Fs = 48 kHz) to run
the serial ports on the SHARCs. Through the AES board
control interface, the SHARCs can reset the AES board,
read/write the punch in/out lines (GPI), set the tally back
data (GPO), select the audio input data (analog or digital),
and set the AES configuration bits (C bits) in the AES
output.
3-2DADR-5000 |
ACEC
