5. OSD Insertion Circuit9. AUTO CHROMA PHASE
The on-screen display of the R-signal is realized byThe signals that are output from IC1401 are selected by
inserting the OSD blanking with IC1300 (2/3) and byIC2380. Only the sample pulse portion of the selected
inserting the OSD with IC1304 (1/3). The WINDOWsignal is sampled by IC2381 and is compared with the
signal that is used during the AUTO W/B adjustment isoutput by IC2382. The error signal from the comparator is
created by the character generator, and uses the samefed back to DAC through IC2383 and automatically
signal line in the same way for character display. Thecontrols the PB LEVEL or the R LEVEL until the output
same insertion operation is performed in the G and Bagrees with the sampled level.
signals in the same way.
10. B1 Board
6. CUT-OFF CircuitThe B1 board is an aperture correction circuit.
CUT-OFF of the R-signal is performed by IC1304 (2/3, 3/The aperture correction performs the frequency compensa-
3). The same cut-off operation is performed in the G andtion at 5 MHz when the input signal is 480/60i and 575/
B signals in the same way.501 with DL400/DL401. It performs the frequency
compensation at 16 MHz when any other signals are input.
7. CXA1739 Peripheral CircuitDL404 and DL405 are the delay lines that corrects the
The RGB signal is input during the normal operation anddelay amount of the Y-signal. The PB and PR signals are
the color difference signal is input during the blue-onlycorrected of their delay amounts by DL501, DL502,
mode.DL503 and DL504.
(The B-signal is input to the Y input connector.)Amount of compensation can be varied by 2 to 6 dB when
CXA1739 has the built-in auto cut-off loop. The auto cut-the APT is ON using the aperture correction amplifier.
off reference pulse is inserted into every H. period in the
order of R, G then B channels at the end of the V. BLKG11. Sync Separator Circuit/B2 Board
period (during the 3H period immediately after the rise-upThe sync separator circuit consists of the sync AGC circuit
of the V. pulse that is supplied to pin-18) in the outputand the B2 board.
signal from CXA1739. The return pulse of the referenceEither the input sync signal in the mode of 480/60i and
pulse is buffered by Q1402 and input to IC1401 pin-25.575/501 or that in any other modes, is selected by IC3301
The return pulse that is input to pin-25 is compared with(2/3), (3/3), Q3302 and Q3303. The sync signal is separat-
the BIAS control voltage by the voltage comparator. Theed by the SYNC AGC circuit of Q3304 to Q3319.
error signal from the comparator is used to shift the DCEither INT sync or EXT sync is selected by IC3301.
output voltage until the return pulse agrees with theIn the B2 board, the equalizing pulses are extracted by
adjustment voltage. This circuit operation is performed toIC3901, the H. sync pulse is separated by the H. SYNC
prevent the changing of the cut-off level caused by the driftSEP. circuit consisting of IC3904, IC3905, IC3906,
of CRT or of the drive circuit.IC3907 and the V. sync pulse is separated by the V. SYNC
Q1431 to Q1434 in the R-signal output circuit remove theSEP. circuit consisting of Q3905, Q3907, Q3908.
smear that occurs inside the IC.The switch IC3902 is the selector switch that selects either
The same circuit operation is performed in the G-channelthe internal sync separator output or the already separated
and the B-channel too.H. and V. sync signals that are input when the SDI signal
is used.
8. ABL Circuit
The ABL circuit consists of Q1460 for ABL and Q1461
for BRT ABL.
The ABL voltage from the deflection block is input the
respective emitters of Q1460 and Q1461. The voltage-
divided DC voltage of the ABL signal is input the respec-
tive bases of Q1460 and Q1461. Their collectors are
connected to IC1401 pin-46 (PIC CONT) and pin-7 (BRT
CONT) respectively. When these transistors are turned on,
the ABL operation can be performed by decreasing their
respective control voltages.
BVM-D14H1U/D14H5U/D14H1E/D14H5E/D14H1A/D14H5A6-5 |
ACEC
