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Section 4
Circuit Description
MAV-70
Recording SystemSystem Control
The video and audio signals input from the BKMA-7010The disk protocol control signal from a host controller is
(encoder/decoder) and/or BKMA-7020 (encoder) areinput from the REMOTE terminal and sent to the DPC
compressed and recorded on SDRAM of a PCI control(disk protocol controller) CPU (IC513) on the SY-253
circuit. The PCI control circuit on the PU-102 boardboard. In the DPC CPU, the disk protocol control signal is
transfers the SDRAM data on each encoder board to thehand-shaked and sent through dual-port RAMs (IC501 and
PU-102 board according to the instructions from theIC529) to the main CPU (IC306) as a command. The
system control block of the MAV-70 and records it on thestatus is sent from the main CPU to the host controller via
HDD array.a reverse route.
The FSE (file system engine) CPU (IC410) manages the
Playback Systemfile system database of the file name on the recorded image
Data is reproduced from the HDD array according to theand the HDDOs LBA data. It is controlled by a command
instructions from the system control block of the MAV-70(file generation, retrieval, or deletion) that is sent from the
and transferred to SDRAM on each decoder board. Themain CPU through dual-port RAMs (IC401 and IC423).
compression data recorded on SDRAM of the BKMA-The CPU (IC101) on the CCM-37 board controls the
7010 (encoder/decoder) and/or BKMA-7030 (decoder) are10Base-T Ethernet standard. IC101 sends a command to
expanded, decoded to video and audio signals, and thenthe main CPU through the dual-port RAMs (IC801 and
output.IC802) on the SY-253 board when the file system is
downloaded or uploaded using a personal computer.
HDD Array BlockMain CPU (IC306) sends a command or receives a status
During recording, on the PU-102 board, the compressionto or from each option board (BKMA-7000 series) or HDD
data sent via a PCI bus is distributed into seven HDDs andarray (PU-102 board) through a PCI controller (IC203)
then recorded. Simultaneously with recording, parity datawhile exchanging commands or status with each CPU
is generated and recorded on the parity HDD.above.
During playback, the data read from seven HDDs is sentThe CPU (IC3) on the DP-269 board of the front panel
through a PCI bus to the decoder. If one HDD can normal-communicates in serial with the main CPU on the SY-253
ly read no data due to failure, the data of the defectiveboard via RS-232C, and sends the key switch information
HDD is recovered based on the data of the parity HDD andor receives the information displayed on the LCD panel.
remaining six HDDs.
MAV-704-1 (E) |
ACEC
