7. BLOCK DIAGRAM8. FLAG No.
No. Flag NameFunction
0MT-OUT Motor Drive Output
1HF-OUT TDA1302T HF signal output
2
3HF-HPF HF Signal HPF Output
4LDONLaser Diode Control Signal
Q102 SAA7372GP5
6RARadial Motor Control Signal(PDM )
7FOFocus Motor Control Signal(PDM )
Q1038SLSlegde Motor Control Signal(PDM )
9
10DIGODigital Audio Output Signal
11CDR7CD7 (SAA7372) Reset Pulse
12SILDCD7(SAA7372) Servo Parte enable Signal
13RAB7CD7 (SAA7372) Decorde and DSP parte enable signal
14SCDCCD7 (SAA7372) data clock out signal
Q10415WCDC CD7 (SAA7372) data word clock out signal
16SIIOServo pcb and Main pcb comunicateing signal
17
18LRCKSM5844AF (Q309) word clock signal
19
20
21DADCCD7 (SAA7372) data out(16bit) signal
2236MHz Sampling frequency 48KHz/32KHz Master clock
2333MHz Sampling frequency 44KHz Master clock
24SDAFrom CPU(QF01) TO TDA1315H(Q304) data signal
25SCLFrom CPU(QF01) TO TDA1315H(Q304) clock signal
26
27RESTCPU (QF01) Power on reset
28RCDKMain pcb SIIO Latch pulse for(Q501,Q502,Q503)
29RCDG SERVO PCB SIIO Latch pulse for QF06
30
31
32
33
34
35OSCCPU (QF01) self clock
36OSCCPU (QF01) self clock
Q304 TDA1315
37
38
39
40
41LOCKTDA1315H (Q304) unlock delayed output signal
42EMPATDA1315H (Q304) Deemphasis output signal
43DACDCD7 (SAA7372) data out signal
44
45
46
47
48DMUT from CPU(QF01) to TDA1315H(Q304) muting signal
49
50FS32TDA1315H(Q304) 32k Sampling detected signal
51FS44TDA1315H(Q304) 44.1k Sampling detected signal
52FS48TDA1315H(Q304) 48k Sampling detected signal
53SDTDA1315H(Q304) data output signal
54WSTDA1315H (Q304) Word select output signal
55SCKTDA1315H (Q304) data clock output signal
56FRQ2CD7 (SAA7372) Operating clock out signal
57 UNLOCK TDA1315H (Q304) unlock output signal
58
59COAX2 Digtal I/O input COAX2 signal
60OPT0Digtal I/O input OPTICAL signal
61
62
63
64
65
66OUT+Correct phase AUDIO SIGNAL
67OUT-Inverse phase AUDIO SIGNAL
68
69REMU Relay mute by POWER ON/OFF and selecting FILTER mode
70
71
72
73
74
75
76
77
78
79768FS Master clock selecting output
80256FS Master clock divided output
81128FS Master clock divided output
824FS176.4KHz before Word select signal
83WSDA Word select for DSP(Q509) and DAC(QD03,QD53) 176.4KHz
84FMUTFilter select switching on time unenable for DAC
85CLDADSP (Q509) data clock signal
86BCENDSP (Q509) data clock enable signal for DAC
87BCDAfor DAC(QD03,QD53) data clock 5.6448MHz
88
89
90
91
92
93
94
95
96
97
98
99
910 |
ACEC
