7321 N/B Maintenance7321 N/B Maintenance
5. Pin Descriptions of Major Components
5.1 Mobile AMD K7 Processor
Detailed Ball Descriptions
Name Description Name Description
A20M# Ball A20M# is an input from the system used to simulate address wrap-around INIT# Ball INIT# is an input from the system that resets the integer registers without
in the 20-bit 8086. affecting the floating-point registers or the internal caches. Execution
AMD Athlon? See the AMD Athlon? and AMD Duron? Processor System Bus starts at 0FFFF FFF0h.
Processor System Bus Specification, order# 21902 for information about the system bus INTR Ball INTR is an input from the system that causes the processor to start an
Balls balls ?PROCRDY, PWROK, RESET#, SADDIN[14:2]#, interrupt acknowledge transaction that fetches the 8-bit interrupt vector
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#, SCHECK[7:0]#, and starts execution at that location.
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#, JTAG Balls TCK (V1), TMS (K3), TDI (W2), TRST# (Y1), and TDO (Y2) are the
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#. JTAG interface. Connect these balls directly to the motherboard debug
Analog Ball Treat this ball as a NC. connector. Pullup TDI, TCK, TMS, and TRST# to VCC_CORE with
CLKFWDRST Ball CLKFWDRST resets clock-forward circuitry for both the system and pullup resistors.
processor. K7CLKOUT and K7CLKOUT (AC19) and K7CLKOUT# (AD19) are each run for 2 to 3
CLKIN and RSTCLK Connect CLKIN (AC16) with RSTCLK (AC17) and name it SYSCLK. K7CLKOUT# Balls inches and then terminated with a resistor pair, 100 ohms to VCC_CORE
(SYSCLK) Balls Connect CLKIN# (AD16) with RSTCLK# (AD17) and name it and 100 ohms to VSS. The effective termination resistance and voltage
SYSCLK#. Length match the clocks from the clock generator to the are 50 ohms and VCC_CORE/2.
Northbridge and processor. NC Balls The motherboard should provide a surface mount pad for all 564 package
balls. The pads for NC balls should not be electrically connected to
See ?SYSCLK and SYSCLK#?, for more information. anything.
CONNECT Ball CONNECT is an input from the system used for power management and NMI Ball NMI is an input from the system that causes a non-maskable interrupt.
clock-forward initialization at reset.
COREFB and COREFB and COREFB# are outputs to the system that provide processor PLL Bypass and Test PLLTEST# (AA3), PLLBYPASS# (AB23), PLLMON1 (AD13),
COREFB# Balls core voltage feedback to the system. Balls PLLMON2 (AC13), PLLBYPASSCLK (AB17), and PLLBYPASSCLK#
CPU_PRESENCE# CPU_PRESENCE# is connected to VSS on the processor package. If (AB16) are the PLL bypass and test interface. This interface is tied
Ball pulled-up on the motherboard, CPU_PRESENCE# may be used to detect disabled on the motherboard. All six ball signals are routed to the debug
the presence or absence of a processor. connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
DBRDY and DBREQ# DBRDY (AB2) and DBREQ# (T4) are routed to the debug connector. PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
Balls DBREQ# is tied to VCC_CORE with a pullup resistor. resistors.
FERR Ball FERR is an output to the system that is asserted for any unmasked PWROK Ball The PWROK input to the processor must not be asserted until all voltage
numerical exception independent of the NE bit in CR0. FERR is an planes in the system are within specification and all system clocks are
open-drain active High signal that must be inverted and level shifted to an running within specification.
active Low signal. For more information about FERR and FERR#, see For more infor mation, s ee ?Signal and Power -Up Requirements?.
the ?Required Circuits? chapter of the AMD Athlon? Processor RSVD Balls Reserved balls must have pulldown resistors to ground on the
Motherboard Design Guide, order# 24363. motherboards.
FID[3:0] Balls The FID[3:0] balls drive a value of: FID[3:0] = 0 1 0 0 SADDIN[1:0]# and The mobile AMD Athlon H-series OBGA processor model 6 does not
that corresponds to a 5x SYSCLK multiplier after PWROK is asserted to SADDOUT[1:0]# Ballssupport SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to
the processor. This information is used by the Northbridge to create the VCC_CORE with pullup resistors, if this bit is not supported by the
SIP stream that the Northbridge sends to the processor after RESET# is Northbridge (future models of the AMD Athlon processors may support
deasserted. SADDIN[1] #) . SADDOUT[1:0]# are tied to VCC_CORE with pullup
For more information, see ?SYSCLK Multipliers?. resistors if these balls are supported by the Northbridge. For more
FLUSH# Ball FLUSH# must be tied to VCC_CORE with a pullup resistor. If a debug information, see the AMD Athlon? and AMD Duron? Processor
connector is implemented, FLUSH# is routed to the debug connector. System Bus Specification, order# 21902.
IGNNE# Ball IGNNE# is an input from the system that tells the processor to ignore
numeric errors. 82 |
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